The WeakReference class, monitoring memory leak and garbage collection in a Java application

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Image
 Below is a Stack implementation that uses an internal resizeable array structure.  public class MyStack< T > implements Stack< T > { private static final int CAPACITY = 100 ; private Object[] array ; private int pos = 0 ; public MyStack () { this . array = new Object[ CAPACITY ] ; } @Override public void push ( T item) { if ( pos >= array . length / 2 ) { Object[] newArray = new Object[ pos * 2 ] ; System. arraycopy ( array , 0 , newArray , 0 , array . length ) ; array = newArray ; } array [ pos ++] = item ; } @Override public T pop () { if (isEmpty()) { throw new RuntimeException( "empty stack" ) ; } @SuppressWarnings ( "unchecked" ) T item = ( T ) array [ pos - 1 ] ; pos -= 1 ; return item ; } @Override @SuppressWarnings ( "unchecked" ) public T peek...
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Running SPEC2000 binaries on SimpleScalar

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Fast-forwarding and limiting the instructions:

Example: fast-forward 1 million instructions and then execute 100 million instructions:

(under simple-sim3.0 directory)

./sim-outorder -max:inst 1000000000 tests/spec2000/164.gzip/gzip00.peak.ev6 input.source 60









sim-outorder 256.bzip2/bzip200.peak.ev6 input.source 58

 sim-outorder 164.gzip/gzip00.peak.ev6 input.source 60

 sim-outorder 164.gzip/gzip00.peak.ev6 2000000: input.source 60

 sim-outorder 2000000: 181.mcf/mcf00.peak.ev6 inp.in

sim-outorder 186.crafty/crafty00.peak.ev6 < crafty.in

sim-outorder 197.parser/parser00.peak.ev6 2.1.dict -batch < 197.parser/ref.in

sim-outorder x175.vpr/vpr00.peak.ev6 < x175.vpr/net.in

sim-outorder 183.equake/equake00.peak.ev6 < 183.equake/inp.in

sim-outorder _177.mesa/mesa00.peak.ev6 < _177.mesa/mesa.in

Percentage of instructions that are fetched from the same page:

int/bzip2: 99%
int/gzip:  99%
int/mcf: 95%
int/crafty: 99%
int/parser: 95%
int/x175.vpr: 95%
float/lukas: 97%
float/equake: %98
float/wupwise: %96
float/mesa: %99
float/art: %93
float/sixtrack: %99 


 [1] Zhao, L. E. I., et al. "A leakage efficient instruction tlb design for embedded processors." IEICE TRANSACTIONS on Information and Systems 94.8 (2011): 1565-1574.


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